1. Field of the Invention
This invention relates generally to a method for forming conductive contacts to different regions of a semiconductor substrate and to the resulting semiconductor device. More particularly, the invention relates to a method of forming contacts with active regions in an MOS transistor or the like, which regions comprise the source region and the drain region, while maintaining electrical isolation between the regions and the gate. The resulting device permits positive self-aligned contact to be made to the source region, drain region and gate of an MOS transistor.
2. Discussion of Background and Prior Art
Metal oxide semiconductor (MOS) devices are well known. Field effect transistors (FET) MOS devices are also well known and are generally referred to as MOSFETs. For example, a p-channel MOSFET consists of a lightly doped n-type substrate into which two highly doped p.sup.+ regions are diffused. One of the p.sup.+ regions is connected to a conductor and is referred to as a source. The other of the p.sup.+ regions is connected to another conductor and is referred to as a drain. Between the source and the drain another conductor is positioned which is known as the gate. The source and the drain are diffused into the silicon and the gate sits atop an insulating layer, generally a silicon dioxide layer. In essence, the gate is charged so as to induce a p-channel between the two separated p.sup.+ regions of the MOSFET. This will produce an enhancement type MOS. N-channel MOSFETs can similarly be constructed.
One problem with the prior art MOSFET devices has been that the diffused doped regions have generally had a relatively high resistance. Another problem with the prior art MOSFETs has been the tight alignment tolerance to the source, gate and drain contacts. Still another problem has been that there has been relatively high overlap capacitance and resulting punch through via the induced channel. Furthermore, polysilicon has often been used as the gate material and this has a relatively high resistance.
Shibata, et al, in an article entitled "An Optimally Designed Process for Submicron MOSFETS" describe a process wherein a platinum silicide layer is plated to the surfaces of the source, drain and gate polysilicon in a self-aligning way to reduce the source or drain resistance and the resistance of the polysilicon interconnect. A CVD SiO.sub.2 layer is deposited after delineation of the gate polysilicon and reactive ion etching of the SiO.sub.2 layer. This results in prism-shaped oxide coverings on the side walls of the polysilicon gates. Platinum silicide layers are formed selectively on the exposed silicon surfaces. The platinum-silicide layer is made by depositing the platinum upon the silicon, heating, and thereby forming the silicide in situ. Thus, this process is limited to silicides which may be formed by rapidly diffusing metals such as platinum and to areas of exposed silicon. These silicides tend to have a relatively higher resistivity than do silicides of refractory metals.